1. Field of the Invention
The present invention relates to transfer of voice information in a packet switching network environment and particularly to transfer of voice-over-Internet Protocol (IP) in a packet switching network environment employing Digital Signal Processors and memory units for storing voice packets to be transferred through the packet switching network.
2. Description of the Prior Art
In modern communications systems it is typical to employ large arrays of DSP (Digital Signal Processors) devices for transmission of data or voice information from one communications device to another. A DSP device is generally an integrated circuit (otherwise referred to as a chip or semiconductor) that is a specialized processor executing code (referred to as firmware or software) to rapidly and efficiently process mathematical functions such as multiply and add operations. For example, a DSP device is capable of executing a multiply and add operation in a single machine cycle (using one clock cycle), which is generally performed at a higher speed and lower cost than when implemented by a general-purpose Central Processing Unit (CPU) or processor.
A common DSP application is a modem which converts voice information, i.e. telephone calls, into digitized packets and vice versa. In this respect, generally, voice information is first digitized (converted from analog format to digital format) prior to being converted to packets. In the analog domain, signals of the type voice, fax or data may be transported. Modern DSP chips can carry multiple data or voice channels. An example of such a communications system is a RAS (Remote Access Server) where large arrays of DSP devices are employed therein implementing hundreds of modems on a single PCB (Printed Circuit Board).
In traditional communications systems, a single (primary) CPU (Central Processing Unit) communicates with a single DSP. The DSP transforms the information into packets and the CPU retrieves each packet of information from the DSP memory and stores each packet in its memory, which may be located internally or externally to the DSP chip, for transmission at a later time. Currently, this process of information retrieval is initiated whenever the DSP device receives a new packet in its memory. Subsequently, the DSP device sends an interrupt prompt over to the CPU which causes the CPU to realize that there is a new packet of information in the DSP memory. The CPU then proceeds to fetch a pointer for identifying the address or location of the new packet of information within the DSP memory. Subsequently, the CPU fetches the new packet of information from the DSP memory. In this manner, the CPU responds whenever it is interrupted by the DSP device. This manner of transporting information is commonly referred to as interrupt-driven PIO (Programmed Input/Output).
Although the PIO approach to information movement works well when the CPU has to support a few DSP devices, as the number of DSP devices increases, a problem arises with managing all of the DSP devices. It is the inventors"" experience that as the number of total voice channels reaches 30 or more, excessive delay or latency develops which renders the PIO approach unsuitable for the service of voice-traffic. This is because as each of the DSP devices receives new information, it must interrupt the CPU while the CPU is busy with other high level tasks. The result may be insufficient time for PIO information movement in-and-out of each DSP device, particularly at the required information transfer rates and latency limits.
Latency is an important issue for systems involving voice communications such as modems, which often need to process multiple voice or data channels in a single chip. A single DSP chip often has throughput limitations imposed by a slow local bus interface. In addition, the interface between the CPU and the point to which information is transferred thereto, such as the Internet in a packet switching network environment, is usually much faster than the DSP interface which further decreases efficiency by requiring the CPU to wait for information to be received from the slower DSP interface.
That is, the rate at which the CPU operates and accesses its local memory for transfer of packets is much faster than the rate at which the DSP device operates and accesses its local memory, which results in a latency issue. For example, voice information is transmitted onto voice channels that are received by DSP devices at a rate of 64 Kbits/sec because each voice channel transfers information to the DSP device at such rate, whereas, voice information transmitted from the CPU (generally through an Ethernet connection) is transferred at 100 Mbits/sec. The need to service hundreds or thousands of slow data streams leads to the problem that the CPU will have in terms of servicing all of the DSP devices. The more DSP devices employed, the more exacerbated this problem becomes.
An alternate approach to PIO data movement which is popularly used is to employ one or more DMA (Direct Memory Access) controllers to transfer data between the DSP memory and the CPU memory, the latter referred to herein as packet memory. In this approach, the DMA controller rather than the CPU moves data from the DSP memory to the packet memory. However, this approach has the same problem as the previous one in that for a few DSPs it is feasible to use a DMA controller for data movement but for a large array of DSPs, containing, for example, more than 96 such units, the exclusive use of DMA controller with no added intelligence is inefficient.
Furthermore, the traditional low-cost DSP does not include a DMA controller. A third alternative might be to implement secondary CPUs for every few DSPs only to handle the low-level data movement, and this is undesirable because it is expensive.
In view of the above, it is desirable to develop a DMA-based architecture wherein the process of moving data in and out of each DSP is made intelligent so that for a system involving a large array of DSPs, which can potentially handle hundreds of voice calls, data is transferred at appropriate rates between the DSP memory and the packet memory with no the CPU to transfer information on a packet-by-packet basis thereby allowing the CPU to offload a substantial burden involving data movement to leave enough time for other high-level tasks.
Briefly, a network device for establishing communication between a first communication unit and a second communication unit through a packet switching network includes a DSP array responsive to signals having coupled thereon voice, fax or data information for digitizing the information and converting the same to packets to form digitized packets of information. The network device further includes a routing engine for transmitting the digitized packets through the packet switching network; a DSP memory coupled to the DSP array for storing said digitized packets; a packets memory coupled to the routing engine for storing a plurality of said digitized packets for transfer thereof to the routine engine; and a memory interface unit coupled between the DSP memory and the packets memory for consummating the transfer of the digitized voice packets from the DSP memory to the packets memory for transfer thereof to the routing engine and accumulating a large number of the digitized packets in the packets memory prior to effectuating the transfer to the routing engine, wherein minimal intervention for transmitting the digitized packet is required by the routing engine thereby allowing the routing engine to tend to higher level tasks resulting in a reduction in voice latency and increased overall system efficiency.
The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description of the preferred embodiments which made reference to the several figures of the drawing.